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IXDF502 / IXDI502 / IXDN502
2 Ampere Dual Low-Side Ultrafast MOSFET Drivers
Features
* Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes * Latch-Up Protected up to 2 Amps * High 2A Peak Output Current * Wide Operating Range: 4.5V to 30V * -55C to +125C Extended Operating Temperature * High Capacitive Load Drive Capability: 1000pF in <10ns * Matched Rise And Fall Times * Low Propagation Delay Time * Low Output Impedance * Low Supply Current * Two Drivers in Single Chip
General Description
The IXDF502, IXDI502 and IXDN502 each consist of two 2Amp CMOS high speed MOSFET Gate Drivers for driving the latest IXYS MOSFETs & IGBTs. Each of the Dual Outputs can source and sink 2 Amps of Peak Current while producing voltage rise and fall times of less than 15ns. The input of each Driver is TTL or CMOS compatible and is virtually immune to latch up. Patented* design innovations eliminate cross conduction and current "shoot-through". Improved speed and drive capabilities are further enhanced by very quick & matched rise and fall times. The IXDF502 is configured with one Gate Driver Inverting plus one Gate Driver Non-Inverting. The IXDI502 is configured as a Dual Inverting Gate Driver, and the IXDN502 is configured as a Dual Non-Inverting Gate Driver. The IXDF502, IXDI502 and IXDN502 are each available in the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the 6-Lead DFN (D1) package, (which occupies less than 65% of the board area of the 8-Pin SOIC).
Applications
* * * * * * * * * * Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Class D Switching Amplifiers Power Charge Pumps
*United States Patent 6,917,227
Ordering Information
Part Number IXDF502PI IXDF502SIA IXDF502SIAT/R IXDF502D1 IXDF502D1T/R IXDI502PI IXDI502SIA IXDI502SIAT/R IXDI502D1 IXDI502D1T/R IXDN502PI IXDN502SIA IXDN502SIAT/R IXDN502D1 IXDN502D1T/R Description 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. 2A Low Side Gate Driver I.C. Package Type 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 6-Lead DFN 6-Lead DFN 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 6-Lead DFN 6-Lead DFN 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 6-Lead DFN 6-Lead DFN Packing Style Tube Tube 13" Tape and Reel 2" x 2" Waffle Pack 13" Tape and Reel Tube Tube 13" Tape and Reel 2" x 2" Waffle Pack 13" Tape and Reel Tube Tube 13" Tape and Reel 2" x 2" Waffle Pack 13" Tape and Reel Pack Configuration Qty 50 Dual, with one 94 Driver Inverting 2500 and one Driver 56 Non-Inverting 2500 50 Dual, with both 94 Drivers 2500 Inverting 56 2500 50 Dual, with both 94 Drivers Non2500 Inverting 56 2500
NOTE: All parts are lead-free and RoHS Compliant
Copyright (c) 2007 IXYS CORPORATION All rights reserved
DS99573B(03/10)
First Release
IXDF502 / IXDI502 / IXDN502
Figure 1 - IXDF502 Inverting + Non-Inverting 2A Gate Driver Functional Block Diagram
Vcc
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P IN A ANTI-CROSS CONDUCTION CIRCUIT *
*
OUT A N
P IN B ANTI-CROSS CONDUCTION CIRCUIT *
*
OUT B N
GND
Figure 2 - IXDI502 Dual Inverting 2A Gate Driver Functional Block Diagram
Vcc
P IN A ANTI-CROSS CONDUCTION CIRCUIT * OUT A N
*
P IN B ANTI-CROSS CONDUCTION CIRCUIT * OUT B N
*
GND
Figure 3 - IXDN502 Dual 2A Non-Inverting Gate Driver Functional Block Diagram
Vcc
P IN A ANTI-CROSS CONDUCTION CIRCUIT * OUT A N
P IN B ANTI-CROSS CONDUCTION CIRCUIT * OUT B N
GND
*
United States Patent 6,917,227
Copyright (c) 2007 IXYS CORPORATION All rights reserved
2
IXDF502 / IXDI502 / IXDN502
Absolute Maximum Ratings (1)
Parameter Supply Voltage All Other Pins Junction Temperature Storage Temperature Lead Temperature (10 Sec)
Value 35V -0.3 V to VCC + 0.3V 150 C -65 C to 150 C 300 C
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Operating Ratings (2)
Parameter Value Operating Supply Voltage 4.5V to 30V Operating Temperature Range -55 C to 125 C Package Thermal Resistance * 8-PinPDIP (PI) J-A (typ) 125 C/W 8-Pin SOIC (SIA) J-A(typ) 200 C/W 6-Lead DFN (D1) J-A(typ) 125-200 C/W 6-Lead DFN (D1) J-C(max) 3.3 C/W 6-Lead DFN (D1) J-S(typ) 7.3 C/W
Electrical Characteristics @ TA = 25 oC (3)
Unless otherwise noted, 4.5V VCC 30V . All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Symbol VIH VIL VIN IIN VOH VOL ROH ROL IPEAK IDC tR tF tONDLY tOFFDLY VCC ICC
Parameter High input voltage Low input voltage Input voltage range Input current High output voltage Low output voltage High state output resistance Low state output resistance Peak output current Continuous output current Rise time Fall time On-time propagation delay Off-time propagation delay Power supply voltage Power supply current
Test Conditions 4.5V VCC 18V 4.5V VCC 18V
Min 3.0
(4) Typ
Max 0.8
Units V V V A V V A A ns ns ns ns V mA A A
-5 0V VIN VCC -10 VCC - 0.025
VCC + 0.3 10 0.025
VCC = 15V VCC = 15V VCC = 15V CLOAD =1000pF VCC =15V CLOAD =1000pF VCC =15V CLOAD =1000pF VCC =15V CLOAD =1000pF VCC =15V 4.5 VIN = 3.5V VIN = 0V VIN = +VCC
2.5 2 2
4 3 1
7.5 6.5 25 20 15 1 0
10 9 32 30 30 3 15 15
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDF502 / IXDI502 / IXDN502
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
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Unless otherwise noted, 4.5V VCC 30V , Tj < 150oC All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Symbol VIH VIL VIN IIN VOH VOL ROH ROL IDC tR tF tONDLY tOFFDLY VCC ICC
Parameter High input voltage Low input voltage Input voltage range Input current High output voltage Low output voltage High state output resistance Low state output resistance Continuous output current Rise time Fall time On-time propagation delay Off-time propagation delay Power supply voltage Power supply current
Test Conditions 4.5V VCC 15V 4.5V VCC 15V
Min 3.1
Typ
Max 0.8
Units V V V A V V A ns ns ns ns V mA A A
-5 0V VIN VCC -10 VCC - 0.025
VCC + 0.3 10 0.025
VCC = 15V VCC = 15V
6 5 1
CLOAD =1000pF VCC=15V CLOAD =1000pF VCC =15V CLOAD =1000pF VCC =15V CLOAD =1000pF VCC =15V 4.5 VIN = 3.5V VIN = 0V VIN = + VCC 15 1 0
11 10 40 38 30 3 40 40
Notes: 1. Operating the device beyond the parameters listed as "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The device is not intended to be operated outside of the Operating Ratings. 3. Electrical Characteristics provided are associated with the stated Test Conditions. 4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the J-A, J-C and J-S values: 1) The J-A (typ) is defined as junction to ambient. The J-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the J-A value supposes the DFN package is soldered on a PCB. The J-A (typ) is 200 C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the J-A by adding connected copper pads or traces on the PCB. These can reduce the J-A (typ) to 125 C/W easily, and potentially even lower. The J-A for DFN on PCB without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management. 2) J-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The J-C values are generally not published for the PDIP and SOIC packages. The J-C for the DFN packages are important to show the low thermal resistance from junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe. 3) The J-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the DFN package.
Copyright (c) 2007 IXYS CORPORATION All rights reserved
4
IXDF502 / IXDI502 / IXDN502
Pin Description
PIN 2 1 3 2 4 3 5 4 6 5 7 6 PACKAGE SOIC, DIP DFN SOIC, DIP DFN SOIC, DIP DFN SOIC, DIP DFN SOIC, DIP DFN SOIC, DIP DFN SYMBOL IN A FUNCTION A Channel Input DESCRIPTION A Channel Input signal-TTL or CMOS compatible. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. B Channel Input signal-TTL or CMOS compatible. B Channel Driver output. For application purposes, this pin is connected via a resistor to a gate of a MOSFET/IGBT. Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 30V. A Channel Driver output. For application purposes, this pin is connected via a resistor to a gate of a MOSFET/IGBT.
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GND
Ground
IN B OUT B VCC OUT A
B Channel Input B Channel Output Supply Voltage A Channel Output
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configuration
IXDF502
1 2 3 4
IXDI502
8 7 6
1 2 3 4
IXDN502
8 7 6
1 2 3 4
NC IN A GND INB
NC O UT A VS
NC IN A GND INB
NC O UT A VS
NC IN A GND INB
NC O UT A VS
8 7 6
O UT B 5
O UT B 5
O UT B 5
8 Lead PDIP (PI) 8 Pin SOIC (SI) (SIA) IXDF402
8 Lead PDIP (PI) 8 Pin SOIC (SI) (SIA) IXDI402
8 Lead PDIP (PI) 8 Pin SOIC (SI) (SIA) IXDN402
6 Lead DFN (D1) (Bottom View)
6 OU A IN A 1 T 5 Vc c GND 2 IN B 3
6 Lead DFN (D1) (Bottom View)
6 OU A IN A 1 T 5 Vc c 4 OU B T GND 2 IN B 3
6 Lead DFN (D1) (Bottom View)
6 OU A T 5 Vc c IN A 1 GND 2 IN B 3
4 OU B T
4 OU B T
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 4 - Characteristics Test Diagram
Vcc
10uF
0.01uF
1 NC 2 In A 3 Gnd 4 In B
NC 8 7 Out A 6 Vcc Out B 5 Agilent 1147A Current Probe 1000 pF Agilent 1147A Current Probe 1000 pF
IXYS reserves the right to change limits, test conditions, and dimensions.
5
IXDF502 / IXDI502 / IXDN502
Typical Performance Characteristics
Fig. 5
80 70 60
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Rise Time vs. Supply Voltage
Fig. 6
Fall Time vs. Supply Voltage
70 60
Rise Time (ns)
Fall Time (ns)
10000pF 50 40 30 20 1000pF 10 560pF 0 0 5 10 15 20 25 30 35 40 5400pF
50
10000pF
40
30
5400pF
20
10
1000pF
0 0 5 10 15 20 25
560pF
30 35 40
Supply Voltage (V)
Fig. 7
Supply Voltage (V)
Fig. 8
Rise / Fall Time vs. Temperature VSUPPLY = 15V CLOAD = 1000pF
Rise Time vs. Capacitive Load
90 80 5V
12
Rise / Fall Time (ns)
10
Rise Time (ns)
Rise time 8 Fall time 6
70 10V 60 50 40 30 20 15V 20V
4
2
10
0 -50 0 50 100 150
0 100
1000
10000
Temperature (C)
Fig. 9
70 5V 60
Load Capacitance (pF)
Fig. 10
2.5
Fall Time vs. Capacitive Load
Input Threshold Levels vs. Supply Voltage
Fall Time (ns)
50
Threshold Level (V)
2
10V 15V 20V
40
1.5
Positive going input Negative going input
30
1
20
0.5
10
0 100
0 0
1000 10000
10
20
30
40
Load Capacitance (pF)
Copyright (c) 2007 IXYS CORPORATION All rights reserved
Supply Voltage (V)
6
IXDF502 / IXDI502 / IXDN502
Fig. 11 Fig. 12
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Input Threshold Levels vs. Temperature
3
Propagation Delay vs. Supply Voltage Rising Input, CLOAD = 1000pF
40
Propagation Delay Time (ns)
Input Threshold Level (V)
2.5
35 30 25 20
Inverting Non-Inverting
2 Positive going input 1.5 Negative going input 1
15 10 5 0
0.5
0 -50 0 50 100 150
0
5
10
15
20
25
30
35
40
Temperature (C)
Fig. 13
Supply Voltage (V)
Fig. 14
Propagation Delay vs. Supply Voltage Falling Input, CLOAD = 1000pF
Propagation Delay Time (ns)
Propagation Delay vs. Temperature VSUPPLY = 15V CLOAD = 1000pF
45
40 35 Negative going input 30 25 Positve going input 20 15 10 5 0
Propagation Delay Time (ns)
40 35 30
Inverting
25 20
Non-Inverting
15 10 5 0 0 5 10 15 20 25 30 35 40
-50
0
50
100
150
Supply Voltage (V)
Fig. 15
Temeprature (C)
Fig. 16
90
Quiescent Current vs Supply Voltage
Quiescent current vs Temperature Vsupply = 15V
35
Quiescent Current (uA)
30 25 20 15 10 5 0 0V 5V 10V 15V 20V 25V 30V 35V inverting input=gnd non-inverting input=vcc
Quescent Current (uA)
80 70 60 50 40 30 20 1 0 0 -55 -25 0 25 50 75 1 00 1 25
inverting input=gnd non-inverting input=vcc
Supply Voltage (V)
7
Temperature (C)
IXDF502 / IXDI502 / IXDN502
Fig. 17
100 90 2MHz
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Supply Current vs. Capacitive Load VSUPPLY = 5V
Fig. 18
Supply Current vs. Frequency VSUPPLY = 5V
10000pF
100 90
Supply Current (mA)
80 70 60 50 40 30 20 10 100kHz 0 100 1000 10000 1MHz
Supply Current (mA)
80 70 60 50 40 30 20 1000pF 10 0 100 560pF 1000 10000 5400pF
Load Capacitance (pF)
Fig. 19
200 180 2MHz
Frequency (kHz)
Fig. 20
200 180 10000pF
Supply Current vs. Capacitive Load VSUPPLY = 10V
Supply Current vs. Frequency VSUPPLY = 10V
Supply Current (mA)
160 140 120 100 80 60 40 20 100kHz 0 100 1000 10000 1MHz
Supply Current (mA)
160 140 120 100 80 60 40 1000pF 20 0 100 560pF 1000 10000 5400pF
Load Capacitance (pF)
Fig. 21
300 2MHz
Frequency (kHz)
Fig. 22
300 10000pF
Supply Current vs. Capacitive Load VSUPPLY = 15V
Supply Current vs. Frequency VSUPPLY = 15V
Supply Current (mA)
200
Supply Current (mA)
250
250
200 5400pF 150
150
1MHz
100
100
50 100kHz 0 100 1000 10000
50
1000pF 560pF
0 100
1000
10000
Load Capacitance (pF)
Copyright (c) 2007 IXYS CORPORATION All rights reserved
Frequency (kHz)
8
IXDF502 / IXDI502 / IXDN502
Fig. 23
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Supply Current vs. Capacitive Load VSUPPLY = 20V
2M Hz
Fig. 24
400 350
Supply Current vs. Frequency VSUPPLY = 20V
10000pF
400 350
Supply Current (mA)
300 250 200 150 100 50 100kHz 0 100 1000 10000 1M Hz
Supply Current (mA)
300 250 200 150 100 1000pF 50 0 100
560pF
5400pF
1000
10000
Load Capacitance (pF)
Fig. 25 Fig. 26
Frequency (kHz)
Output Sink Current vs. Supply Voltage
0 -1
Output Source Current vs. Supply Voltage
7 6
Source Current (A)
Sink Current (A)
5
-2
4
-3
3
-4
2
-5
1
-6
0 0 5 10 15 20 25 30 35 40
-7 0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Fig. 27
3.5
Supply Voltage (V)
Fig. 28
0
Output Source Current vs. Temperature VSUPPLY = 15V
Output Sink Current vs. Temperature V SUPPLY = 15V
Output Source Current (A)
2.5
Output Sink Current (A)
-50 0 50 100 150
3
-0.5
-1
2
-1.5
1.5
-2
1
-2.5
0.5
-3
0
-3.5 -50 0 50 100 150
Temperature (C)
9
Temperature (C)
IXDF502 / IXDI502 / IXDN502
Fig. 29
6
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High State Output Resistance vs. Supply Voltage
Fig. 30
Low State Output Resistance vs. Supply Voltage
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
5
4
3
2
1
0 0 5 10 15 20 25 30 35
Output Resistance (ohms)
Output Rsistance (ohms)
0
5
10
15
20
25
30
35
Supply Voltage (V)
Supply Voltage (V)
Copyright (c) 2007 IXYS CORPORATION All rights reserved
10
IXDF502 / IXDI502 / IXDN502
Supply Bypassing, Grounding Practices And Output Lead inductance
When designing a circuit to drive a high speed MOSFET utilizing the IXD_502, it is very important to observe certain design criteria in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXD_502 to charge a 1500pF capacitive load from 0 to 25 volts in 25ns. Using the formula: I = C V/t, where V=25V C=1500pF & t=25ns, we can determine that to charge 1500pF to 25 volts in 25ns will take a constant current of 1.5A. (In reality, the charging current won't be constant, and will peak somewhere around 2A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXD_502 must be able to draw this 1.5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected and should have low inductance, low resistance and high-pulse currentservice ratings). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXD_502 to an absolute minimum.
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GROUNDING In order for the design to turn the load off properly, the IXD_502 must be able to drain this 1.5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXD_502 and its load. Path #2 is between the IXD_502 and its power supply. Path #3 is between the IXD_502 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXD_502. OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and its load as short and wide as possible. If the driver must be placed farther than 0.2" (5mm) from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load.
11
IXDF502 / IXDI502 / IXDN502
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A2 b b2 b3 c D D1 E E1 e eA eB L
E
H B C D E e H h L M N
D A e B A1
h X 45 N L M C
0.157 0.005 [3.99 0.13]
0.020 [0.51]
0.039 [1.00]
0.019 [0.49]
0.197 0.005 [5.00 0.13]
0.035 [0.90]
0.137 [3.48]
S0.002^ 0.000; o S0.05^ 0.00;o
[
]
0.018 [0.47]
IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de
0.100 [2.54]
0.120 [3.05]
Copyright (c) 2007 IXYS CORPORATION All rights reserved
12

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